Integrated circuits (ICs) are fabricated on wafers of a semiconductor material such as silicon. As many integrated circuit devices as possible are placed on the wafer to maximize the number of devices fabricated per wafer and reduce the cost per finished device.
The IC device contains semiconductor devices, such as transistors, capacitors and resistors, formed on the silicon substrate. The electrical connections used to hook up the semiconductor devices to form a working device are known in the art as “interconnects”. Interconnects consist of metal lines formed in the plane of the substrate, and vias formed in the direction normal to the plane of the substrate. Several interconnect levels may be used in the IC, with highly integrated microprocessors using eight or more levels.
A special case of the via level is that level connecting the first metal level to the semiconductor devices. These vias are known as “contacts,” and are formed by a process that is different than the vias between metal levels. Contacts are typically formed from tungsten, with certain layers lining the contact to getter contaminants, act as a barrier, and to form an ohmic contact to the semiconductor devices.
High quality contacts are essential to high device yield and reliability, but fabrication of these high quality contacts poses several technical challenges. For example, the contacts are designed to have a high ratio of the height to the diameter, known as the aspect ratio. High aspect ratio is a consequence of several constraints in the design of the IC. For example, it is desirable to achieve a high packing density of the contacts to enable high circuit density. This constrains the diameter of the contacts to be as small as possible. In addition, the dielectric separating the semiconductor devices from the first metal level must be thick enough to protect transistors from mobile metal ions. Moreover, the deepest contact is as deep as the sum of the thickness of the dielectric over the transistor and the height of the transistor gate over the semiconductor substrate. These constraints lead to contacts with aspect ratios large enough to present manufacturing challenges.
One such challenge is removing contaminants from the bottom of the contact hole before depositing one or more barrier layers into the hole. Contamination has the effect of increasing the contact resistance, Rc, of the contact and reducing device reliability. In conventional practice, the contamination is partially removed prior to deposition of one or more films by performing a presputter etch (PSE). The PSE is typically an argon plasma formed under conditions that favor the sputtering and ejection of material from the bottom of the contact hole. To some extent, however, the PSE also knocks dielectric material off the sidewall of the contact hole, which redeposits onto the bottom of the hole. Thus, there is a competition between removal of contamination from the bottom of the hole and redeposition of sidewall material. Proper design of the PSE process will minimize the net contamination at the bottom of the hole, but generally some contamination will remain, raising the contact resistance above the level that would otherwise be obtainable.
Another critical challenge is the ability to deposit continuous films into the contact hole. In conventional practice, a liner is deposited, followed by a barrier. The liner serves to getter contaminants and to promote adhesion of a barrier deposited over the liner. The liner films may be deposited using a physical deposition process such as Physical Vapor Deposition (PVD) or Ionized Metal Plasma (IMP) deposition. Such processes preferentially deposit onto the top surface of the dielectric, and to a lesser extent at the bottom of the contact hole. However, the deposited film thins out particularly on the sidewalls of the contact hole. Moreover, the thickness of the liner material deposited at the bottom of the contact hole decreases as the aspect ratio increases, leading to a risk of reduced effectiveness in the gettering of contaminants at the bottom of the contact hole.
Similar issues are confronted in obtaining continuous barrier coverage of the contact sidewalls. For some choices of liner material, a continuous barrier is critical to producing high quality devices with high yield. An example is the use of Ti as the liner, which will react with the tungsten precursor, typically WF6, during contact formation if gaps in the barrier exist. This reaction results in yield-limiting defects and poor reliability.
Yet another critical manufacturing challenge is forming the contact plug without seams and voids. Contact seams can lead to increased contact resistance and decreased reliability. A tungsten CVD process is typically used to form the plug, and under appropriate conditions, seams and voids can form in the plug. These seams and voids will typically form when the contact hole has a reentrant profile, i.e., when the contact hole diameter increases with increasing depth of the hole, over at least a portion of the hole. Even if the contact sidewalls are not reentrant after the hole is formed, deposition of the liner can result in a shoulder of material at the top of the hole which results in the undesirable profile. The resolution of these manufacturing issues is critical to producing ICs with high yield to keep the manufacturing cost as low as possible.
Accordingly, what is needed is a method of forming contact liner and barrier layers which addresses the challenges outlined above.